Computer arrangements, including microprocessors and digital signal processors, have been designed for a wide range of applications and have been used in virtually every industry. Significant advancements are continually sought in circuit miniaturization, performance and speed through the development of very large-scale integrated circuits. These complex circuits are often designed as a plurality of functional units interconnected by a shared digital data communications path, each functional unit processing a set, or packet, of data, then passing the processed data on to other functional units for further data manipulations. A functional unit is often a source of new data, generated in response to received data or commands.
Data packets in large and small quantities are communicated between functional units, for example, between individual discrete circuits, between integrated circuits on a common chip, or between remotely-located circuits coupled to or within various parts of a system or subsystem. Regardless of the configuration, the communication typically requires closely-controlled interfaces that are designed to ensure that data integrity is maintained while using circuit designs are sensitive to practicable limitations in terms of implementation space and available operating power. An increased demand for high-speed semiconductor devices must address not only performance of the functional units themselves, but also the speed and efficiency by which data is passed between the functional units.
Typically, digital data paths are implemented using parallel data transmission channels, or busses. Multiple data bits are sent simultaneously over “parallel bussing,” a well-accepted approach for achieving higher data transfer rates. A typical parallel digital-data path is implemented in various forms, including a cable, a backplane circuit, a bus structure internal to a chip, other interconnect, or any combination of such communication media. The plurality of digital data packets, moving between functional units sharing the digital data path, are collectively referred to as “traffic,” distantly analogous to vehicular traffic sharing a common highway interconnecting numerous geographic destinations. However, in parallel communications, only one device can communicate over the digital data path at a time; the device essentially commandeers the entire digital data path and broadcasts data to every other device. Those devices needing the broadcast data accept it, and those not needing the broadcast data ignore it.
Computer system modifications sometimes increase communication traffic to an existing digital data path. This increase is helpful to test an existing system prior to finalizing (and frequently prior to beginning) design of modification to determine if the system can support additional bus traffic, and the extent to which additional bus traffic is tolerable. Additionally, performance of the modification's effect on the digital data path and/or the modification's effect on the balance of the system are conventionally tested as an integral step of a design process. For example, one testing method includes loading the digital data path with additional bus traffic simulating a proposed modification's new use of the digital data path, and evaluating system performance under the loaded conditions.
Currently, a system designer's options for simulating additional bus traffic are limited to routing the new bus traffic through the system's microprocessor, or an unoccupied direct memory access (DMA) channel. These options include inherent limitations on the type and amount of bus traffic that can be generated through each particular traffic source. Frequently, a DMA channel is not available and system microprocessors are generally already fully utilized performing other processing operations. Using microprocessor power to generate additional simulated bus traffic decreases the microprocessor's speed at which other tasks are accomplished. System test results are therefore inherently erroneous, not only reflecting effects due to the additional bus traffic, but also effects attributable to the decreased microprocessor attention to routine and background tasks while in bus-traffic-simulation mode.
With an ongoing demand to increase digital data path (bus) throughput, there is a need for a testing circuit and method dedicated to generating additional bus traffic of any type which will further address the aforementioned problems, as well as other related problems. The present invention is directed to a circuit and method for performing the above-mentioned bus traffic generation operations while increasing availability and minimizing processing burden on existing bus access resources.